The invention concerns a multi-channel controller.
Communication controllers need to handle a large number of communication channels. In each of the communication channels, data is sent in packets of variable size. The packets include transmit packets and receive packets. Transmit packets are packets of data which are sent from the communication controller to the communication channels and receive packets are packets of data which are sent from the communication channels to the communication controller. A receive packet is usually buffered within a memory storage element of the communication controller and then is sent to the communication controller central processing unit (i.e.xe2x80x94CPU), in order to be processed. A transmit packet is usually buffered within memory bank of the communication controller before being sent to a communication channel. In prior art arrangement each received packet was sent to the CPU, and the CPU handled one packet at a time. The CPU also handled a single transmit packet at a time.
In many cases the packet length (e.g.xe2x80x94the number of bits of the packet) PL was much smaller than the CPU""s size (e.g.xe2x80x94the number of data bits a CPU can read in a single clock cycle) CS. When a CPU handles just a single packet at a time, it reduces the CPU performances. For example, a packet length could be 2, 4 or 8 bits while the CPU""s size is 16, 24, 32 or 64 bit. If a 32-bit CPU handles just 2 bits at a time, the remaining 30-bits of the CPU are not utilized.
Furthermore, a CPU usually handles a packet as a result of an interrupt. A communication controller can handle a limited number of interrupt requests. Handling a single packet in a interrupt request, limits the number of packets the communication controller can handle.
When an interrupt is sent to the CPU, it is usually accompanied by various data and status fields. When dealing with multiple communication channels, the CPU has to be fed with a label which indicates what is the relevant communication channel. When receiving data from a communication channel, the CPU also need to read the received data. Usually, the status and data are stored in queues. If the receive queue (which stores both status and data) is the same as the transmit queue (which stores status), a significant part of the transmit queue is wasted. There is a need to design a efficient queues, which can store status bits (transmit queue) and store both status and data (receive queue) in a efficient way.
When an interface, such as but not limited to a communication controller, receives (transmits) PL-bit data packets, and transmits (receives) CS-bit data to a receiver, such as but not limited to a processor, there is a need to detect when CS bits were received from a communication channel. When the interface is coupled to multiple communication channels it is very difficult to count the bits of each channel, and alternatively, having a dedicated counter which counts the number of bits received from each communication channel is very die consuming. There is a need of an efficient interface which can receive (transmit) PL-bit data packets from (to) multiple communication channels and transmit (receive) CS-data bit words to a receiver, such as but not limited to a processor.
There is a need of a communication controller which handles in an efficient manner a plurality of data packets which are sent from multiple communication channels.